1. Field of the Invention
The present invention relates to a fabricating method of a flat panel display device, and more particularly to a fabricating method of a flat panel display device that can reduce its manufacturing cost.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) device controls a light transmittance of liquid crystal in accordance with a video signal, thereby displaying a picture. To this end, the liquid crystal display device includes a liquid crystal display panel where liquid crystal cells are arranged in a matrix shape, and a drive circuit for driving the liquid crystal display panel.
The liquid crystal display device is mainly divided into two modes in accordance with the direction of an electric field in which a liquid crystal is driven: a twisted nematic (TN) mode where a vertical electric field is applied and an in-plane switch (IPS) mode where a horizontal electric field is applied.
The TN mode is a mode of driving the liquid crystal by a vertical electric field between a pixel electrode of a lower substrate and a common electrode of an upper substrate that face each other. The TN mode has an advantage of a high aperture ratio, but its viewing angel is narrow. On the other hand, the IPS mode is a mode of driving the liquid crystal by a horizontal electric field between a pixel electrode and a common electrode that are arranged parallel to each other on a lower substrate. The IPS mode has an advantage of a wide viewing angle, but its aperture ratio is low.
FIG. 1 is a cross-sectional view representing a TN mode liquid crystal display panel according to the related art.
Referring to FIG. 1, the liquid crystal display panel includes an upper array substrate where a black matrix 54, a color filter 56, a common electrode 68 and an upper alignment film 58 are sequentially formed on an upper substrate 52; a lower array substrate where a TFT, a pixel electrode 66 and a lower alignment film 88 are formed on a lower substrate 82; and a liquid crystal 16 injected into an inner space between the upper array substrate and the lower array substrate.
In the upper array substrate, the black matrix 54 provides a cell area where the color filter 56 is to be formed, prevents light leakage and absorbs external light so as to increase the contrast ratio. The color filter 56 is formed in the cell area that is divided by the black matrix 54. The color filter 56 includes R, G and B color filter layers to display color images on the liquid crystal display panel. A common voltage is supplied to the common electrode 68 for controlling the movement of the liquid crystal 16. For the IPS mode where a horizontal electric field is applied, the common electrode 68 is formed on the lower array substrate.
In the lower array substrate, the TFT includes a gate electrode 59 formed on the lower substrate 82 together with the gate line (not shown); a semiconductor layer 64, 97 overlapping the gate electrode 59 with a gate insulating film 94 therebetween; and a source and drain electrode 90, 92 formed together with the data line (not shown). The TFT supplies a pixel signal from the data line to the pixel electrode 66 in response to a scan signal from the gate line.
The pixel electrode 66 is formed of a transparent conductive material with a high light transmittance ratio and is in contact with a drain electrode 92 of the TFT with a passivation film 100 therebetween. Upper and lower alignment films 58, 88 for aligning the liquid crystal 16 are formed by performing a rubbing process after spreading an alignment material such as polyimide.
The thin film patterns including the gate electrode 59 of the liquid crystal display panel are mainly formed by a photolithography process using a mask. FIGS. 2A to 2D are cross-sectional views illustrating a step by step formation of a gate electrode using a photolithography process.
Referring to FIG. 2A, a gate metal 59a and a photoresist 60 are deposited on the lower substrate 82 by a deposition method such as sputtering, and a mask 61 having an aperture is aligned with areas where the gate electrodes 59 are to be formed. Then, an exposure process and a development process are performed to form a photoresist pattern 60a shown in FIG. 2B, an etching process is performed to pattern the gate electrode 59 as shown in FIG. 2C. Finally, the gate electrode 59 is completed by a stripping process as shown in FIG. 2D.
Generally, a photolithography process includes depositing a photoresist, aligning a mask, exposing the photoresist to light and developing the photoresist, and etching the subject using the photoresist. Thus the photolithography process is complicated and a developing solution for developing the photoresist pattern is wasted. Also, the exposure process requires expensive equipment.